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Ordering number : ENN6198A
LB1928
Monolithic Digital IC
LB1928
Three-Phase Brushless Motor Driver for Office Automation Equipment
Overview
The LB1928 is a 3-phase brushless motor driver well suited for drum and paper feed motors in laser printers, plain-paper copiers and other office automation equipment. Direct PWM drive allows control with low power losses. Peripheral circuitry including speed control circuit and FG amplifier is integrated, thus allows drive circuit to be constructed with a single chip.
Package Dimensions
unit: mm 3147B-DIP28H
[LB1928]
28 15
R1.7
12.7 11.2
8.4
1
20.0 27.0
14
Functions and Features
* * * * * * * Three-phase bipolar drive (30V, 3.1A) Direct PWM drive technique Built-in diode for absorbing output lower-side kickback Speed discriminator and PLL speed control Speed lock detection output Built-in forward/reverse switching circuit Built-in protection circuitry includes current limiter, overheat protection, motor restraint protection, etc.
1.93
1.78
0.6
1.0
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter Maximum supply voltage Maximum output current Allowable power dissipation 1 Allowable power dissipation 2 Operating temperature Storage temperature Symbol Vcc max IO max Pd max 1 Pd max 2 Topr Tstg Conditions T 500 ms IC only With an arbitrary large heat sink Ratings 30 3.1 3 20 -20 to +80 -55 to +150 Unit V A W W C C
Allowable Operating Ranges at Ta = 25C
Parameter Power supply voltage range 1 Regulator voltage output current LD output current Symbol Vcc IREG ILD Conditions Ratings 9.5 to 28 0 to -20 0 to 15 Unit V mA mA
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
D1099TH(KI)/73099RM(KI) No. 6198-1/11
4.0
4.0
SANYO : DIP28H
0.4
LB1928
Electrical Characteristics at Ta = 25C, Vcc = VM = 24V
Parameter Power supply current 1 Power supply current 2 [Output block] Output saturation voltage 1 Output saturation voltage 2 Output leak current Lower-side diode forward voltage 1 Lower-side diode forward voltage 2 [5V regulator voltage output] Output voltage Voltage fluctuation Load fluctuation [Hall amplifier] Input bias current Common mode input voltage range Hall input sensitivity Hysteresis width Input voltage L -> H Input voltage H-> L [PWM oscillator] Output High level voltage Output Low level voltage Oscillator frequency Amplitude [CSD circuit] Operating voltage External capacitance charge current Operating time [Current limiter operation] Limiter [Thermal shutdown operation] Thermal shutdown operating temperature Hysteresis width [FG amplifier] Input offset voltage Input bias current Output High level voltage Output Low level voltage FG input sensitivity Next-stage Schmitt comparator width Operating frequency range Open-loop gain [Speed discriminator] Output High level voltage Output Low level voltage Count number [PLL output] Output High level voltage Output Low level voltage [Lock detection] Output Low level voltage Lock range Symbol Icc1 Icc2 Vosat1 Vosat2 Ioleak V D1 V D2 VREG VREG1 VREG2 IHB VICM VIN VSLH VSHL VOH(PWM) VOL(PWM) f(PWM) C = 3900 pF V(PWM) VOH(CSD) ICHG t(CSD) VRF TSD TSD VIO(FG) IB(FG) VOH(FG) VOL(FG) IFGO = -0.2 mA IFGO = 0.2 mA Gain 100 times Design target value f(FG) = 2 kHz 2.5 1.2 1.05 3.6 -17 C = 10 F Design target value VCC-VM Design target value (junction temperature) Design target value (junction temperature) 0.45 150 Conditions min Ratings typ 23 3.5 2.0 2.6 1.2 1.5 4.65 5.00 30 20 -0.5 VREG -1.5 24 12 -12 2.8 1.5 18 1.30 3.9 -12 3.3 0.5 180 50 +10 +1 VREG -0.8 0.8 180 51 VREG -0.7 0.8 512 VREG -1.5 1.5 0.15 6.25 3.1 1.8 1.55 4.2 -9 42 max 30 5 2.5 3.2 100 1.5 2.0 5.35 100 100 Unit mA mA V V A V V V mV mV A V mVp-p mV mV mV V V kHz Vp-p V A s V C C mA A V 1.2 250 2 V mV mV kHz dB
In STOP mode Io = 1.0A, Vo(SINK) + Vo(SOURCE) Io = 2.0A, Vo(SINK) + Vo(SOURCE) ID = -1.0A ID = -2.0A Io = -5 mA Vcc = 9.5 to 28V Io = -5 to -20 mA
-2 1.5 80 15
0.55
-10 -1 VREG -1.2 3 100 45 VREG -1.0
VOH(D) VOL(D)
IDO = -0.1 mA IDO = 0.1 mA
V 1.1 V
VOH(P) VOL(P) VOL(LD)
IPO = -0.1 mA IPO = 0.1 mA ILD = 10 mA
VREG -1.8 1.2
VREG -1.2 1.8 0.5
V V V %
Continued on next page
No. 6198-2/11
LB1928
Continued from preceding page Parameter [Integrator] Input bias current Output High level voltage Output Low level voltage Open-loop gain Gain bandwidth product Reference voltage [Crystal oscillator] Operating frequency range Low level pin voltage High level pin current [Start/stop pin] High level input voltage range Low level input voltage range Input open voltage Hysteresis width High level input current Low level input current [Forward/reverse pin] High level input voltage range Low level input voltage range Input open voltage Hysteresis width High level input current Low level input current Symbol Conditions Ratings min -0.4 VREG -1.2 typ max +0.4 Unit A V 1.2 V dB kHz V MHz V mA V V V V A A V V V V A A
IB(INT) VOH(INT) VOL(INT) IINTO = -0.2 mA IINTO = 0.2 mA f(INT) = 1 kHz Design target value Design target value
VREG -0.8 0.8 45 51 450 -5% VREG/2 3
5% 10
fOSC VOSCL IOSCH VIH(S/S) VIL(S/S) VIO(S/S) VIN IIH(S/S) IIL(S/S) VIH(F/R) VIL(F/R) VIO(F/R) VIN IIH(F/R) IIL(F/R)
IOSC = -0.5 mA VOSC = VOSCL + 0.3V 3.5 0 VREG -0.5 0.35 -10 -280 3.5 0 VREG -0.5 0.35 -10 -280
1.65 0.4 VREG 1.5 VREG 0.50 0 -210 0.65 10
V(S/S) = VREG V(S/S) = 0V
VREG 1.5 VREG 0.50 0 -210 0.65 +10
V(F/R) = VREG V(F/R) = 0V
No. 6198-3/11
LB1928
Truth Table
Source 1 2 3 4 5 6 Sink OUT2 -> OUT1 OUT3 -> OUT1 OUT3 -> OUT2 OUT1 -> OUT2 OUT1 -> OUT3 OUT2 -> OUT3 IN1 H H H L L L F/R = "L" IN2 L L H H H L IN3 H L L L H H IN1 L L L H H H F/R = "H" IN2 H H L L L H IN3 L H H H L L
Pin Assignment
OUT1
28
F/R
27
IN3+ IN3- IN2+ IN2- IN1+ IN1- GND1
26 25 24 23 22 21 20
S/S FGIN+ FGIN- FGOUT LD
19 18 17 16 15
LB1928
1 2 3 4 5 6 7 8 9 10 11 12 13 14
OUT2 OUT3 GND2 VCC
VM
VREG PWM CSD
XI
XO INTOUT INTIN POUT DOUT Top view
Pd max - Ta
24
Allowable power dissipation, Pd max - W
With an arbitrary large heat sink
20
16
12
8
4 3 0 -20
Without heat sink
0
20
40
60
80
100
120
Ambient temperature, Ta - C
Relationship between crystal oscillator frequency fosc and FG frequency fFG is as follows. fFG (servo) = fosc/ (ECL divide-by-16 x count number) = fosc/8192
No. 6198-4/11
LD
FGIN- POUT
-
FGOUT I NT. OUT CSD INT AMP PWM
LD
DOUT I NT.IN
FG AMP
-
FGIN+
LOCK DET TSD SPEED DISCRI LIM
Rf VM Vcc
+
VREG/2
+
CSD CIRCUIT PWM OSC
Equivalent Circuit Block Diagram
-
CURR
Vcc
+
VREG COMP
FG PLL
OUT1
LB1928
RST
VREF 1/512 BGP HALL HYS AMP S/S F/R 5VREG VREF LOGIC
GND1
ECL
1/16
DRIVER
OUT2
Xtal
OSC
OUT3
XI
XO
S/S
F/R
VREG
I N1
I N2
I N3
GND2
No. 6198-5/11
LB1928
Pin Description
Pin number 28 1 2 3 5 Pin name OUT1 OUT2 OUT3 GND2 VM Equivalent circuit
VCC 300 VM 5
1
2
28
3
A12983
Pin function Motor drive output pins. Connect a Schottky diode between these outputs and VCC. Output ground pin. Output block power supply and output current detection pin. Connect a resistor (Rf) between this pin and VCC to detect the output current as a voltage. The output current is limited according to the equation IOUT = VRF/Rf. Power supply pin (except for output block) Regulated power supply output pin (5V output) Connect a capacitor (approx. 0.1 F) between this pin and ground to stabilize the output.
4 6
VCC VREG
VCC
6
A12984
7
PWM
VREG
200 7 2k
PWM frequency setting pin. Connect a capacitor between this pin and ground. C = 3900 pF results in a frequency of about 18 kHz.
A12985
8
CSD
VREG
300 8 1k
Lock protection circuit operation time setting pin. Connecting a capacitor of about 10 F between this pin and ground results in a protection circuit operation time of about 3.3 seconds.
A12986
9 10
XI XO
VREG
10 9
Quartz oscillator pins. Connect to quartz oscillator to generate the reference clock. When an external clock (of several MHz) is used, the clock signal should be input via a resistor of about 5.1 k connected in series with the XI pin. In this case, the XO pin must be left open.
A12987
Continued on next page
No. 6198-6/11
LB1928
Continued from preceding page
Pin number 11 Pin name INT OUT Equivalent circuit
VREG
Pin function Integrator output pin (speed control pin)
11
40k
PWM comparator
A12988
12
INT IN
VREG
Integrator input pin.
300 12
A12989
13
POUT
VREG
PLL output pin.
300 13
A12990
14
DOUT VREG
Speed discriminator output pin. Acceleration: High, Deceleration: Low
300 14
A12991
15
LD
VREG 15
Speed lock detection pin. When motor rotation is within lock range (6.25%): Low Withstand voltage: 30V max.
A12992
Continued on next page
No. 6198-7/11
LB1928
Continued from preceding page
Pin number 16 Pin name FG OUT Equivalent circuit
VREG
Pin function FG amplifier output pin.
16
40k
FG schmitt comparator
A12993
17 18
FGIN- FGIN+
VREG
20k
FG reset circuit 300 18
20k
FG amplifier input pin. By connecting a capacitor (approx. 0.1 F) between FGIN+ and ground, the logic circuitry is reset.
300 17
A12994
19
S/S
VREG
22k
Start/stop control pin. Start (Low): 0V to 1.5V Stop (High): 3.5V to VREG High when open. Hysteresis width: approx. 0.5V.
2k 19
A12995
20 22 21 24 23 26 25
GND1 IN1+ IN1- IN2+ IN2- IN3+ IN3-
VREG
300 21 23 25
300 22 24 26
Ground pin (except for output block). Hall input pins. High when IN+ > IN-, Low when IN+ < IN-. Hall signal should have an amplitude of at least 100 mVp-p (differential operation). When Hall signal noise is a problem, connect a capacitor between IN+ and IN-.
A12996
27
F/R
VREG
22k
Forward/reverse control pin. Forward (Low): 0V to 1.5V Reverse (High): 3.5V to VREG High when open. Hysteresis width: approx. 0.5V.
2k 27
A12997
No. 6198-8/11
LB1928
Description of the LB1928 1. Speed control circuit The IC performs speed control through combined use of a speed discrimination circuit and PLL circuit. The speed control circuit counts FG cycles and outputs a deviation signal every 2 FG cycles. The PLL circuit outputs a phase deviation signal every FG cycle. The FG servo frequency is determined by the following equation. The motor rotation speed is set by the number of FG pulses and the crystal oscillator frequency. fFG (servo) = fOSC/8192 fOSC: Crystal oscillator frequency 2. Output drive circuit In order to reduce power loss at the output, the LB1928 uses the PWM drive technique. While ON, the output transistors are always saturated, and motor drive power is adjusted by varying the output ON duty ratio. Because output PWM switching is performed by the lower-side output transistor, a Schottky diode must be connected between OUT and VCC. (If the reverse recovery time of the diode is too long, a feedthrough current will flow at the instant when the lower-side transistor goes ON.) An internal diode is provided between OUT and GND. If large output current causes a problem (waveform distortion during lower-side kickback, etc.), an external rectifying diode or Schottky diode should be connected. The output diode is integrated only on the lower side. 3. Current limiting circuit The current limiting circuit limits the peak current to the value I = VRF/Rf (VRF = 0.5 V typ., Rf: current detector resistance). Current limiting is achieved by reducing the ON duty ratio of the output, which reduces the current. 4. Power save circuit In order to reduce current drain in the STOP condition, the IC goes into power save mode. In this condition, bias current to most circuits is cut off, but the 5V regulator output remains active. 5. Reference clock The reference clock for speed control can be input using one of the following two methods. [1] Using a crystal oscillator When a crystal is used for oscillation, connect the crystal, capacitors, and a resistor as shown in the figure below.
XI C3 C1 R1 VREG C2
XO
C1, R1: For stable oscillation C3: For crystal coupling C2: For overtone oscillation prevention
No. 6198-9/11
LB1928
(Reference values) C3 (pF) R1 () 47 330k 47 330k 22 330k
Oscillator frequency (MHz) 3 to 5 5 to 8 8 to 10
C1 (F) 0.1 0.1 0.1
C2 (pF) 10 None None
The circuit configuration and values are for reference only. The crystal oscillator's characteristics as well as the possibility of floating capacitance and noise due to layout factors must be taken into consideration when designing an actual application. [Precautions for wiring layout design] Since the crystal oscillator circuit operates at high frequencies, it is susceptible to the influence of floating capacitance from the circuit board. Wiring should be kept as short as possible and traces should be kept narrow. When designing the external circuitry, pay special attention to the wiring layout between the oscillator and C3 (C2), to minimize the influence of floating capacitance. [2] External clock input (equivalent to crystal oscillator, several MHz) When using an external signal source instead of a crystal oscillator, the clock signal should be input from the XO pin through a resistor of about 5.1 k connected to the pin in series. The XO pin should be left open. Signal input level Low : 0 to 0.8V High : 2.5 to 5.0V 6. Speed lock range The speed clock range is 6.25% of the rated speed. When the motor rotation is within the lock range, the LD pin becomes Low (open collector output). When the motor rotation goes out of the lock range, the ON duty ratio of the motor drive output is varied according to the amount of deviation to bring the rotation back into the lock range. 7. PWM frequency The PWM frequency is determined by the capacitance connected to the PWM pin. . f PWM = 1/(14400 x C) . The PWM frequency should be between 15 and 25 kHz. 8. Hall input signal The Hall input requires a signal with an amplitude of at least the hysteresis width (42 mV max.). Taking possible noise influences into consideration, an amplitude of at least 100 mV is desirable. 9. Forward/reverse switching Forward/reverse switching of motor rotation is carried out with the F/R pin. If this is performed while the motor is running, the following points must be observed: * Feedthrough current during switching is handled by proper circuit design. However, the VCC voltage rise during switching (caused by momentary return of motor current to power supply) must not exceed the rated voltage (30V). If problems occur, the capacitance between VCC and GND must be increased. * If the motor current after switching exceeds the current limiter value, the lower-side transistors go OFF but the upper-side transistors go into the short brake state, which causes a current flow. The magnitude of the current is determined by the motor counterelectromotive voltage and the coil resistance. This current may not exceed the rated current (3.1A). (Forward/reverse switching at high speed therefore is not safe.)
No. 6198-10/11
LB1928
10. Motor restraint protection circuit To protect the IC and the motor itself when rotation is inhibited, a restraint protection circuit is provided. If the LD output is High (unlocked) for a certain interval in the start condition, the lower-side transistors are turned off. The length of the interval is determined by the capacitance at the CSD pin. A capacitance of 10 F results in a set interval of about 3.3 seconds. (Tolerance approx. 30%) . Set interval (s) = 0.33 x C (F) . If the capacitor arrangement is subject to leak current, possible adverse effects such as setting time tolerances must be taken into consideration. When the restraint protection circuit has been activated, the condition can only be canceled by setting the system to the stop condition or by turning the power off and on again (in the stop condition). When wishing not to use the restraint protection circuit, connect the CSD pin to ground. If the stop time when releasing the restraint protection is short, the capacitor charge will not be fully dissipated. This in turn will cause a shorter restraint protection activation time after the motor has been restarted. The stop time should therefore be designed to be sufficiently long, using the equation shown below (also when restarting in the motor start transient state). Stop time (ms) 15 x C (F) 11. Power supply regulation Because this IC has a high output current, power supply line fluctuations can occur easily. Therefore a capacitor of sufficient capacitance must be connected between the VCC pin and ground to assure stable operation. If a diode is used in the power line for reverse-connection protection, the likelihood of power line fluctuations increases further, which will require more capacitance.
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of December, 1999. Specifications and information herein are subject to change without notice. PS No. 6198-11/11

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